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We are on a path to improve our world, our future, to make a difference. Join our team and become a part of that difference.

At Oppstar, we continually recruit for top talent and invest in our workforce to fuel diversity, professional and personal growth, and innovation. With more than 150 employees and more than half of them are on clients' site, our strong retention rate is well beyond the industry standard, truly representative of our strong employee engagement and inclusive culture.  

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Advanced Design Verification Engineer

Posted on 24 May 2021

Bayan Lepas, Penang, Malaysia

Responsibilities:

  • Candidate is responsible to verify various IP blocks and full-chip of FPGA/ASIC designs.

  • The job scope includes test plan definition, SystemVerilog/UVM test bench and content development, debugging and running regression to deliver good-quality design.

  • Candidate will work closely with product/IP architect, logic design engineer, DFX owner, and design automation engineer to ensure high quality design validation.

Education & Experience: 

  • Bachelor or Master degree in E&E or Computer Engineering. 

  • A minimum of 4 years relevant working experience.

  • Station in Penang, Kuala Lumpur or able to be relocated to countries within Asian Region for e.g. 1-2 years.

  • Able to converse in Arabic, Japanese or Mandarin language is a plus.

 

 

Qualifications:

  • Familiar with IP protocols (e.g. HSST, Ethernet, PCIe, DDR), FPGA and/or ARM architectures.

  • Demonstrated technical expertise in functional verification of complex designs that includes test planning, test bench development, stimulus generation, reference model and assertion checkers development and functional coverage.

  • Experience with modern verification techniques e.g. SystemVerilog OVM/UVM, assertion-based verification, constrained random verification methodologies.

  • Hands-on experience in various logic designs and verification tools and flow e.g. from Cadence, Mentor Graphics and/or Synopsys.

  • Familiar with other tools and methodology e.g. formality, linting or GLS is a plus.

  • Familiar with Linux OS and proficient in scripting using e.g. Perl, Python or C++.

  • Demonstrated the ability to work independently and within a team environment.

  • Strong technical writing and communication.

Physical Design Engineer

Posted on 12 May 2021

Kuala Lumpur, Malaysia

Responsibilities:

  • Carry out physical implementation works for advanced Soc/ASIC designs from SYN to GDS

  • The job scope includes pathfinding, debugging, and running a regression to deliver good-quality design.

  • The candidate will work closely with team members, and interact with product/IP architect, logic design engineer, DFX owner, and design automation engineer to ensure job delivery on time.

  • Willing to travel (domestic/international), or relocation

Education & Experience: 

  • Bachelor's or Master's degree in E&E or Computer Engineering. 

  1. Advanced: minimum of 4 years relevant working experience

  2. Senior: minimum of 7 years relevant working experience.

  • Able to converse in Arabic, Japanese, or Chinese language is a plus.

 

 

Qualifications:

  • Familiar in block/Sub-system-level physical implementations from SYN to GDS; 

  • Hands-on experience with industrial standard EDA tools and flow e.g. Cadence and/or Synopsys. (superuser is a plus)

  • Experienced in synthesis, floorplanning, clock tree, static timing analysis, signal integrity, EM/IR analysis, ECO implementation, formality verification and physical design verification (DRC, Density, Antenna, LVS)

  • Hands-on experienced in clock gating and power gating design methodology

  • Familiar with Linux OS and proficient in scripting using e.g. shell, tcl, Perl, Python or C++.

  • Demonstrated the ability to work independently and within a team environment.

Physical Design Engineer

Posted on 12 May 2021

Bayan Lepas, Penang, Malaysia

Responsibilities:

 

  • Carry out physical implementation works for advanced Soc/ASIC designs from SYN to GDS

  • The job scope includes path finding, debugging and running regression to deliver good-quality design.

  • Candidate will work closely with team members, and interact with product/IP architect, logic design engineer, DFX owner, and design automation engineer to ensure job delivery on time.

  • Willing to travel (domestic / international), or relocation.

Education & Experience:

 

  • Bachelor or Master degree in E&E or Computer Engineering.

  • Fresh graduate with relevant major is encouraged to apply

  • Junior: 2-3 years relevant working experience

  • Advanced: minimum of 4 years relevant working experience

  • Senior: minimum of 7 years relevant working experience.

  • Able to converse in Arabic, Japanese or Chinese language is a plus.

 

 

Qualifications:

 

  • Familiar in block/Sub system level physical implementations from SYN to GDS;

  • Hands on experience with industrial standard EDA tools and flow e.g. Cadence and/or Synopsys. (super user is a plus)

  • Experienced in synthesis, floorplanning, clock tree, static timing analysis, signal integrity, EM/IR analysis, ECO implementation, formality verification and physical design verification (DRC, Density, Antenna, LVS)

  • Hands on experienced in clock gating and power gating design methodology

  • Familiar with Linux OS and proficient in scripting using e.g. shell, tcl, Perl, Python or C++.

  • Demonstrated the ability to work independently and within a team environment.

Senior/Staff Validation Engineer

Posted on 2 May 2021

Bayan Lepas, Penang, Malaysia

This position is responsible for Hardware Validation and Debug related activities covering the various features of SoC, GPU, FPGA, etc for silicon validation, and debug. 

 

Responsibilities will include but not be limited to:

  • Develop Silicon validation test strategies, plans, and schedules by integrating different requirements from various engineering and business departments.

  • Designing and developing validation tools to support the latest validation technologies and methodologies including validation automation, BIOS, platform driver, debug tool, and others

  • Drive execution of test plans and procedures.

  • Executing validation test suites to identify failures in the platform which may include FPGA, SoC, GPU, chipset board level, and others. 

  • Performing platform level debug by root causing failures and identifying failing components 

  • Collaborate on PCB board design to develop high-speed engineering board and generate test measurement patterns vectors for characterization 

  • Perform bench measurements for high-speed devices using state-of-the-art characterization equipment

  • Plan scheduling of weekly tasks for meeting medium and long-term validation deliverables. Monitor progress against schedule communicating status.

  • Drive exploration of new IP validation methodology platform and infrastructure enablement to improve process and throughput.

 

Qualifications:

  • Master's / Bachelors' degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent experience in the related field. 

  • 5-8+ years of experience with Post Silicon Debug, Validation, and/or Emulation.

  • Hardware validation experience.

  • Experience in a Windows/macOS driver environment.

  • Device Driver and Kernel level debugging.

  • RTL debug.